In contemporary communication systems operating at ever-increasing transmission rates, return-to-zero (RZ) signaling has become a popular method for data exchange. In RZ signaling, a strong component of the clock frequency exists in the data spectrum, providing a reference on which a phaselocked loop (PLL)-based, or filter-based, clock recovery unit (CRU) can latch in order to recover the clock signal from the received data stream. Such PLL-based CRU systems are well-studied and characterized in the technical literature.
At relatively low data transfer rates, a fundamental oscillator is commonly deployed in the PLL, and the recovered clock is obtained directly. In cases where half the clock frequency is desired, for example in demultiplexer applications, a frequency divider is often employed. At higher frequencies, fundamental high-Q oscillators are difficult to build, and are therefore costly, due to the reduction in resonator size. While a frequency doubler can be used, a more compact and relatively low power approach is to employ a harmonic mixer as the phase detector for the phaselocked loop.
In any phaselocked loop application, there are tradeoffs between operation parameters such as phase noise, settling speed, tracking range, stability, loop gain, loop bandwidth, etc. For best performance, an optimum loop transfer characteristic, or combination thereof, can be determined and needs to be maintained. Unfortunately, in some RZ signaling communication systems, the level of the reference tone in the data spectrum can vary over a 10:1 dynamic range, or even more. At the same time, in order to maintain constant and optimal loop performance, this change in signal level cannot be allowed to alter the loop response.
With reference to the schematic block diagram of FIG. 1, a conventional clock recovery unit 50 includes an amplifier 20 and a phaselocked loop 48. The amplifier 20 may comprise, for example, an automatic gain control (agc) amplifier, a linear amplifier, or a limiting amplifier. The received input signal 30, for example in the form of an RZ, or non-return-to-zero (NRZ) serial data stream is amplified by the amplifier 20 and is presented to the phaselocked loop 48. Assuming the amplifier 20 is a limiting amplifier or agc amplifier, the amplifier properties are such that the amplitude variation of the input signal is reduced in the amplified signal 21.
The phaselocked loop 48 includes a phase detector 22, for example in the form of a mixer, an active loop filter 24, and an oscillator 26. The phase detector 22 receives the amplified input signal and a feedback signal 34 and provides a phase difference signal 23 indicative of the difference in phase between the feedback and amplified signals 34, 21. The phase difference signal 23 is filtered by the active loop filter 24, which controls the dynamic performance of the phaselocked loop 48, for example the acquisition and tracking parameters of the phaselocked loop. At high frequencies, the active loop filter 24 typically comprises an analog filter, while at lower signal transfer rates, the active loop filter 24 may comprise a digital filter in the form of a digital signal processor. While an active loop filter is most common, a passive filter, for example in the form of an RCL network is equally applicable. In either case, the filter is optimized to trade off phaselocked loop dynamics including noise performance, stability, pull-in range, and acquisition time. The filtered output signal 25 is presented to an oscillator 26 to adjust the oscillation frequency of the phaselocked loop 48. The oscillator 26 is typically tuned to the expected clock frequency of the input data stream 30. The output of the oscillator 26 is provided as the recovered clock signal 32 and is also fed back via feed back signal 34 to the phase detector 22.
The conventional approach for handling dynamic range variance exhibited by the input data stream is to employ an automatic gain control (agc) amplifier 20 at the reference frequency, for example the RZ carrier frequency, prior to processing by the PLL phase detector 22 as shown in FIG. 1. A number of drawbacks are associated with this approach. First, providing gain at the carrier rate can be expensive and power hungry, for example at the current 20 or 40 GHz RZ signaling rates. Second, if the reference clock tone level varies while the total power in the data spectrum remains constant, the detector in the agc loop will not respond properly, exposing the PLL phase detector to large variations in the tone level. Additionally, due to non-linearities in the phase detector and gain-control elements, a high-gain feedback loop is required to complete the agc circuitry, the dynamic response of which must be carefully optimized.
An alternative approach is to employ a limiting amplifier 20 at the reference frequency for amplifying the received input data steam 30, prior to the PLL phase detector. Although this is the most common approach, it carries with it a number of drawbacks. First, with the entire data spectrum entering into the limiter, rather than a single tone, the limiter, being non-linear, will generate intermodulation products that are likely to appear within the bandwidth of the phaselocked loop. Second, the limiter removes all amplitude information from the processed input signal without providing a signal strength indicator, thereby eliminating a vital error signal source in the RZ system. Additionally, in a poor signal-to-noise environment, the limiter suppresses the desired carrier due to the noise dominating the limiting action.
Another option is to employ a digital phase-frequency detector instead of a balanced mixer phase detector. At the present time, no such digital detectors are available at operation rates above approximately 1.5 GHz. Additionally, such digital systems have associated with them all the drawbacks of the limiter discussed above, creating intermodulation products and stripping amplitude information from the processed input data stream.
Another possibility is to employ a narrow band agc loop at the reference frequency. However, this approach requires a high-Q resonator at the reference frequency, duplicating, to a large degree, the function of the phaselocked loop.
The present invention is directed to a system and method for clock recovery by which a clock signal is recovered from an input data signal in a manner that preserves the signal strength of the input signal. The measure of signal strength, referred to herein as the xe2x80x9csignal strength indicatorxe2x80x9d, is in turn used to normalize the output of the phase detector of the phaselocked loop (PLL), and the normalized signal is used as an input to the PLL oscillator to recover the clock signal from the input data signal. In this manner, the PLL is used to perform narrow band filtering, while relatively inexpensive baseband components are used to compensate for reference signal power variations. The net result is a clock recovery system in which PLL performance remains constant over a wide range of input signal levels, and remains constant with rapidly varying input signal levels. The system is thus more tolerant of transmission link impairments, and can therefore operate at higher data transmission rates and over longer distances.
In one aspect, the present invention is directed to a clock recovery system for recovering a clock signal from an input data signal. The system comprises a primary phase detector for receiving an input data signal, and for combining the input data signal with a feedback signal to generate a phase difference signal. An auxiliary phase detector receives the input data signal and combines the input data signal with the feedback signal to generate the signal strength indicator. A gain equalizer normalizes the phase difference signal by the signal strength indicator, and an oscillator provides the clock signal based on the normalized phase difference signal and further provides the clock signal as the feedback signal which is returned to the auxiliary and primary detectors.
In a preferred embodiment, a first amplifier receives and amplifies the input data signal. The first amplifier preferably comprises a linear amplifier. The input data signal may comprise, for example, a return-to-zero (RZ) signal.
A first splitter may be included for distributing the input data signal to the primary and auxiliary phase detectors. A second splitter may be included for distributing the feedback signal to the primary on auxiliary phase detectors. In a preferred embodiment, the first and second splitters comprise 3 dB splitters.
A filter may be provided for filtering the phase difference signal to control the dynamic performance of the clock recovery system. A temperature compensation unit may be provided for compensating for temperature variance in the system. The temperature compensation unit adjusts the normalized signal phase output signal based on system temperature variance.
The recovered clock signal is preferably presented at an output node. A third splitter distributes the recovered clock signal to the output node as the clock signal and to the primary and auxiliary harmonic mixers as the feedback signal. The third splitter may comprise a 3 dB splitter. A first isolator may be included at an input of the third splitter, and a second isolator at an output of the third splitter that provides the feedback signal, for isolating the system from load variations occurring in a load coupled to the output node, and for preventing corruption of the clock signal by the primary and auxiliary phase detectors.
The gain equalizer preferably comprises a divider for dividing the phase difference signal by the signal strength indicator. The auxiliary phase detector may comprise a harmonic mixer or a combination of a frequency doubler and mixer. A phase shifter may be provided for shifting the phase of the feedback signal to provide a phase-shifted feedback signal to the auxiliary phase detector.
In another aspect, the present invention is directed to a phaselocked loop for locking an output signal to an input signal. A primary phase detector receives an input signal and combines the input signal with a feedback signal to generate a phase difference signal. A gain equalizer normalizes the phase difference signal by a signal strength indicator generated as a function of the signal strength of the input signal. An oscillator provides the output signal based on the normalized phase difference signal and provides the output signal as the feedback signal.
An auxiliary phase detector may be provided for receiving the input data signal and for mixing the input data signal with the feedback signal to generate the signal strength indicator.
In a preferred embodiment, the normalization function is performed at baseband, while the phase detectors and linear input amplifier functions are performed at the carrier band rates.
In this manner, an economical and precise clock recovery system and method are provided. A linear, constant-gain amplifier is employed at the reference frequency, a phaselocked loop is used to perform the narrowband filtering, and a baseband open-loop feed-forward age is used to compensate for reference and signal power variations. This configuration results in a clock recovery system and method in which PLL performance remains constant over a wide range of input signal amplitude levels, and which preserves information regarding the strength of the clock tone which can be used as an error signal in other circuits controlling other devices and subsystems in the receiver.